1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device that can store at least 2 bits of data in each memory cell.
2. Description of Related Art
A semiconductor memory device stores data at a designated address. A typical dynamic random access memory (DRAM) includes a plurality of memory cells, each of which stores 1 bit of data. Each of the memory cells includes a cell transistor and a storage capacitor to store the 1 bit of data or read the stored data. Also, each of the memory cells includes a sense amplifier to amplify data transferred through the cell transistor from the storage capacitor.
Meanwhile, the design rule of memory devices is being reduced to store more data in a given area. To accomplish such a reduction, the resolution of photolithography of a semiconductor fabrication process must first be improved. However, such an increase in the resolution of the photolithography process is reaching a technical limit. Specifically, to increase the resolution, a short-wavelength light source should be used when forming a photoresist pattern. Further, to use the short-wavelength light source, it is necessary to develop new photoresist that reacts desirably to the short-wavelength light source.
Recently, there's been a great deal of research into overcoming the foregoing problems and improving the memory size of a memory device without reducing the design rule.
A multi-level cell DRAM, under study lately, is a memory that can store at least 2 bits of data in each memory cell. That is, memory size can be at least doubled without decreasing a conventional design rule.
In the foregoing multi-level cell DRAM, each memory cell should include a coupling capacitor to store at least 2 bits of data.
Japanese Patent Laid-open Publication No. 11-330272 discloses structures of a multi-level cell DRAM and a coupling capacitor. In this disclosure, coupling capacitors are arranged in series, and adjacent coupling capacitors are connected using a contact plug and a bit line.
Also, Korean Registered Patent No. 231404 introduces structures of a multi-level cell DRAM and a coupling capacitor. In this disclosure, coupling capacitors are connected in series, and adjacent coupling capacitors are connected using a contact plug and a gate electrode.
However, the above disclosures fail to provide a method of controlling the capacitance of the coupling capacitor during a fabrication process. Specifically, the capacitance of the coupling capacitor should be, for example, about 1/9 or ⅓ the capacitance of a storage capacitor for storing data, depending on the type of a cell structure. However, the capacitance of the coupling capacitor, which is separately formed in an isolation region, cannot be maintained in appropriate proportion to the capacitance of the storage capacitor. That is, the capacitance of the coupling capacitor may vary with various variables during sequentially performed processes.